1. Field of the Invention
The present invention relates to a buffer circuit equipped with power sources having different voltages and including CMOS inverter circuits as logical gate circuits, or to an integrated circuit equipped with such a buffer circuit.
2. Description of Related Art
Since portable apparatuses, such as portable telephones and notebook-sized personal computers, are generally powered by batteries, such apparatuses are requested to have low power consumption so as to withstand extended use. Hence, each of integrated circuits being used in these apparatuses is divided into blocks for each function. Depending on the usage condition of such an apparatus, power is supplied only to a functional block required for the operation of the apparatus at the time, whereby power saving is attained.
Such an integrated circuit is configured to use power sources having voltages different depending on the function of the integrated circuit to lower the power voltages to the utmost extent and to reduce power consumption. Hence, the integrated circuit is equipped with a buffer circuit for signal interface between circuits that uses power sources having different voltages.
FIG. 1A is a circuit diagram showing the configuration of a conventional buffer circuit (designated by numeral 200). For example, an output signal from a functional block (not shown), operating on a drive voltage VDD1, for attaining a predetermined function inside an integrated circuit 100 is inputted to the buffer circuit 200. On the other hand, the buffer circuit 200 outputs an output signal to another functional block (not shown) operating on a drive voltage VDD2 lower than VDD1. In this case, the buffer circuit 200 has a voltage step-down circuit for stepping down the drive voltage of the integrated circuit 100 from the high voltage VDD1 to the low voltage VDD2. In this kind of buffer circuit 200, the output of an inverter circuit 210 connected to a power source VD1 having the high voltage VDD1 is connected to the input of an inverter circuit 220 connected to a power source VD2 having the low voltage VDD2.
FIG. 1B is a circuit diagram showing the specific circuit configurations of the two inverter circuits 210 and 220 shown in FIG. 1A. The inverter circuit 210 is composed of a P-channel FET 211 whose source is connected to the power source VD1, and an N-channel FET 212 whose source is connected to a drain of the FET 211. A drain of the FET 212 is grounded. Gates of the two FETs 211 and 212 are connected to each other and serve as the input terminal of the inverter circuit 210. Furthermore, a connection node of the drain of the FET 211 and the source of the FET 212 serves as the output terminal of the inverter circuit 210.
Similarly, the inverter circuit 220 is composed of a P-channel FET 221 whose source is connected to the power source VD2, and an N-channel FET 222 whose source is connected to a drain of the FET 221. The drain of the FET 222 is grounded. Gates of the two FETs 221 and 222 are connected to each other and serves as the input terminal of the inverter circuit 220. Furthermore, a connection node of the drain of the FET 221 and the source of the FET 222 serves as the output terminal of the inverter circuit 220.
In the integrated circuit 100 equipped with such buffer circuit 200, the power sources VD1 and VD2 are repeatedly turned ON and OFF depending on the operation state of the integrated circuit 100, for example, in the case that the power source VD1 is turned OFF to stop the operation of the functional block operating on the power source VD1 or in the case that the power source VD2 is turned OFF to stop the operation of the functional block operating on the power source VD2. This reduces the power consumption of the circuit.
Furthermore, Japanese Patent Application Laid-open No. 2000-341110 has proposed a CMOS transistor circuit in which an output of a first inverter circuit powered by a first power source is connected to an input of a second inverter circuit powered by a second power source, characterized in that an output of a third inverter circuit to which the first power source is inputted and which is powered by the second power source is connected to a gate of an N-channel FET, a drain of the N-channel FET is connected to the output of the first inverter circuit, and a source of the N-channel FET is grounded. In this kind of conventional technology, even in the case that the voltage of the first power source is lowered to the ground level, through current flows the second inverter circuit is prevented, whereby power consumption can be reduced.
However, since the power sources are turned ON or OFF depending on the operation state of the functional block inside the integrated circuit in the above-mentioned conventional technology, an unnecessary current is generated in the CMOS inverter circuit when the power sources are turned ON or OFF, thereby causing a problem of increasing power consumption.
FIG. 2A, FIG. 2B and FIG. 2C are time charts showing operation states of the conventional buffer circuit 200 at the time of power-ON. FIG. 2A shows the changes in the voltages of the two power sources VD1 and VD2, FIG. 2B shows the ON/OFF states of the two FETs 221 and 222 of the inverter circuit 220, and FIG. 2C shows the state of through current flowing the two FETs 221 and 222.
In the case that the power source VD1 is turned ON while the power source VD2 (voltage VDD2) is supplied to the buffer circuit 200 shown in FIG. 1, there is a period in which the voltage of the power source VD1 is lower than the voltage of the power source VD2. For example, when the voltage at the input terminal of the inverter circuit 210 is 0V, the FET 211 turns ON, whereby the voltage Va at the input terminal of the inverter circuit 220 becomes equal to the voltage of the power source VD1 and rises as the voltage of the power source VD1 rises.
At time ta, the voltage of the power source VD1 reaches a threshold voltage Vth of the FET 222, and the FET 222 turns ON. Next, at time tb, the voltage of the power source VD1 reaches a voltage obtained by subtracting the threshold voltage Vth of the FET 221 from the voltage VDD2, and the FET 221 turns OFF. Hence, the two FETs 221 and 222 are in the ON state in the period between time ta and time tb, whereby an unnecessary through current flows the two FETs 221 and 222, and the power consumption increases.
FIG. 3A, FIG. 3B and FIG. 3C are time charts showing other operation states of the conventional buffer circuit 200 at the time of power-ON. FIG. 3A shows the changes in the voltages of the two power sources VD1 and VD2, FIG. 3B shows the ON/OFF states of the two FETs 221 and 222 of the inverter circuit 220, and FIG. 3C shows the state of through current flowing the two FETs 221 and 222.
In the case that the power source VD1 (voltage VDD1) and the power source VD2 (voltage VDD2) are turned ON simultaneously and the voltages are supplied to the buffer circuit 200 shown in FIG. 1, since the rising of the voltage of the power source VD2 is faster than the rising of the voltage of the power source VD1, there is a period in which the voltage of the power source VD1 is lower than the voltage of the power source VD2. For example, when the voltage at the input terminal of the inverter circuit 210 is 0V, the FET 211 turns ON, whereby the voltage Va at the input terminal of the inverter circuit 220 becomes equal to the voltage of the power source VD1 and rises as the voltage of the power source VD1 rises.
At time tc, the voltage of the power source VD1 reaches the threshold voltage Vth of the FET 222, and the FET 222 turns ON. Next, at time td, the voltage of the power source VD1 reaches the voltage obtained by subtracting the threshold voltage Vth of the FET 221 from the voltage VDD2, and the FET 221 turns OFF. Hence, both the two FETs 221 and 222 are in the ON state in the period between time tc and time td, whereby an unnecessary through current flows the two FETs 221 and 222, and the power consumption increases.
Furthermore, in the CMOS transistor circuit disclosed in the above-mentioned Japanese Patent Application Laid-open No. 2000-341110, in the case that the voltage of the first power source is lowered to the ground level, the second power source connected to the third inverter circuit is grounded via the third inverter circuit and the N-channel FET both being in the ON state, whereby an extra current may flow when the first power source is turned ON or OFF.